1. Field of the Invention
The present invention relates to an ESD (electrostatic discharge) protection device, and particularly to an ESD protection device coupled between two high power lines.
2. Description of the Prior Art
As the technology of manufacturing ICs (integrated circuits) advances, the elements in the ICs are more susceptible to outside surroundings and tend to be damaged, especially in an ESD event. In order to protect the ICs from being damaged by an ESD current, ESD protection devices have to be installed in the ICs. Before the elements inside the ICs are damaged by an ESD stress, the ESD protection devices must be timely triggered and conduct the ESD current so as to protect the elements in the ICs.
During IC designing, not only the ESD event accross an I/O port and a power line, but also the ESD event across every two pins of the ICs has to be considered.
In the present design, due to the consideration of noise separation or operation speed, different circuit groups of the ICs may be powered by different power lines from different power sources. For example, I/O circuits are powered by power lines of 3.3 Volt, but core circuits are powered by the power lines of 1.8 Volt. Without adequate ESD protection design between two power lines for different power source, ESD current might damage the interface circuits between the two circuit groups operating with different voltages.
FIG. 1 is a perspective diagram of a prior art ESD protecting system. VDD1 and VSS1 represent a pair of power lines, and VDD2 and VSS2 represent another pair of power lines. Different pairs provide power to different circuits. An ESD_pass circuit 8 is coupled between VDD1 and VDD2, and another ESD_pass circuit 8 is coupled between VSS1 and VSS2. Each of the ESD_pass circuits has to be turned off in normal operation. When an ESD event occurs or the difference between the voltages at two ends is great enough, the ESD_pass circuit will be turned on and current will pass through therein.
The ESD_pass circuit of FIG. 1 is consisiting of two diodes, in which the cathode of one diode is connected to the anode of the other diode. When the voltage difference between the two ends of the ESD_pass circuit is less than a turn-on voltage of a diode in the ESD_pass circuit, the ESD_pass circuit will be turned off, acting as an open circuit. In contrast, when the voltage difference between the two ends of the ESD_pass circuit is greater than the turn-on voltage, the ESD_pass circuit will be turned on, acting as a short circuit to pass current. Choosing the turn-on voltage of the diode depends on the acceptable voltage difference across the two ends of the ESD_pass circuit in normal operation. The greater the acceptable voltage difference is, the greater the turn-on voltage of a diode in the ESD_pass circuit must be. An equivalent diode with a higher turn-on voltage is composed of a number of diodes connected in series. Generally speaking, the turn-on voltage for a single diode fabricated by silicon process is about 0.7 Volt.
However, in the semiconductor manufacturing process, the area required by a single diode is considerable; let alone a plurality of diodes are connected in series. Therefore, in the ESD protecting system of FIG. 1, a considered area on the wafer might be required and increases the cost.
Therefore, the objective of the present invention is to provide an ESD protection device occupying a small area on the wafer and being capable of isolating two power lines. During an ESD event, the two power lines are connected and have low impedances.
According to the present invention, an ESD protection device is coupled between a first high power line and a second high power line. The ESD protection device comprises a N-type well and a P-type well adjacent to each other, and a pair of PN MOS. The N-type well is coupled to the first high power line, and the P-type well is coupled to a low power line. The pair of PN MOS comprises a P-type metal-oxide-semiconductor transistor (PMOS) and a N-type metal-oxide-semiconductor transistor (NMOS). The PMOS is installed in the N-type well, and comprises a first gate structure, a first P-type doped area and a second P-type doped area. The first gate structure is a gate of the PMOS. The first P-type doped area is coupled to the first high power line. The NMOS is installed in the P-type well, and comprises a second gate structure, a first N-type doped area and a second N-type doped area. The second gate structure is a gate of the NMOS. The gate of the NMOS is coupled to the gate of the PMOS to form an input end of the pair of PN MOS. The second P-type doped area is coupled to the second N-type doped area to form an output end of the pair of PN MOS. The first N-type doped area is coupled to the second high power line. In normal operation, either the PMOS or the NMOS is turned off.
The advantage of the invention is that in the pair of the PN MOS, a parasitical silicon controlled rectifier (SCR) is formed and coupled between the first and the second high power lines. In an ESD event, the equivalent resistance of a turned-on SCR is considerably low, and therefore, the SCR can be a well-functioned ESD protection device. Furthermore, the trigger voltage (or the turn-on voltage) of the SCR is adjustable in a layout manner. When a high trigger voltage is needed, the area occupied by the SCR is much smaller than that occupied by the plurality of diodes connected in series. Therefore, the cost of the wafer will be reduced.